Sources of electrical mismatch

Electrical mismatch describes the loss of DC power that occurs when cells, modules, or strings operate under unequal electrical or optical conditions. It manifests at three hierarchical levels:

• Cell-to-cell mismatch — between individual cells in a module
• Module-to-module mismatch — between modules connected in series within a string
• String-to-string mismatch — between strings connected in parallel within an array

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How mismatch is calculated in SunSolve Yield

SunSolve computes mismatch losses from first principles using combined ray tracing and SPICE-based electrical solving.

1. Cell-to-cell mismatch is determined for all modules. The loss equals the difference between:

   • the sum of each cell’s maximum independent power, and
   • the module’s actual maximum power when cells are electrically connected.

2. Module-to-module mismatch is included when string solving is enabled. The loss equals the difference between:

   • the sum of each module’s independent maximum power, and
   • the maximum power of the combined string.

3. String-to-string mismatch is included when multiple strings are connected in parallel to an inverter. The loss equals the difference between:

   • the sum of each string’s independent maximum power, and
   • the maximum array power delivered to the inverter.

This hierarchical solving approach enables SunSolve to quantify mismatch at any scale — from individual cells to entire PV arrays.

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Real sources of electrical mismatch

Mismatch can arise from a wide range of physical and operational effects that cause differences in current, voltage, or resistance across connected elements.

1. Illumination differences

• Shading of direct or diffuse sunlight (row-to-row, near-field objects, or terrain)
• Edge effects, where outer modules receive more sky and ground view
• Cloud transients creating short-term non-uniform irradiance
• Non-uniform soiling (dust, bird droppings, water marks)
• Rear-side non-uniformity due to:
  • Uneven ground reflectance or albedo
  • Structural shading (posts, torque tubes, rails, frames)
  • Varying inter-row spacing or ground conditions

2. Temperature differences

Temperature non-uniformity causes local variations in current and voltage. It can result from:

• Uneven irradiance (as above)
• Variable wind exposure across the array
• Unequal radiative coupling to sky and ground
• Heat conduction differences near frames, supports, or racking

3. Manufacturing and aging variation

• Natural variability in cell or module characteristics
• Mixing of module types or power ratings in the same string
• Uneven degradation, potential-induced degradation (PID), or hot-spot effects

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Simulation-level behaviour in SunSolve

SunSolve explicitly models illumination-driven mismatch (Section 1) by combining optical and electrical solvers:

1. Ray tracing — determines per-cell irradiance for both front and rear surfaces.
2. Circuit solving — calculates IV characteristics for each cell, module, and string using SPICE-based models.
3. Aggregation — computes total DC power at module, string, and array levels, isolating mismatch losses automatically.

This approach ensures that optical shading, albedo variation, and structural effects are accurately translated into electrical mismatch outcomes.

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Stochastic variation in numerical solving

A secondary contributor to apparent mismatch is stochastic error from the ray-tracing process itself. When too few rays are traced relative to the number of cells, random sampling can produce artificial irradiance variation that appears as mismatch.

This is not a physical effect but a numerical artefact. Increasing the ray count reduces these errors.

For more information, refer to the Stochastic Error page.

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Effects not currently modelled

SunSolve assumes identical electrical characteristics for all cells and modules. Therefore, the following are not explicitly included:

• Intrinsic variation in Rs, Rsh, or J₀
• Non-uniform cell or module temperatures
• Degradation or soiling that varies spatially over time
• Electrical imbalance due to mixed module technologies or bin classes

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